1. Field of the Invention
The present invention relates to contacts and interconnect layers in a nonvolatile semiconductor memory. More specifically, it relates to a nonvolatile semiconductor memory and a method for fabricating the same, which is used for interconnects and contacts aligned with minimum fabrication dimensions, such as the contacts, data transfer lines, or via contacts of NAND EEPROMs or NOR EEPROMs.
2. Description of the Related Art
FIGS. 1 through 8 show the contacts and interconnect layers of an example of conventional NAND EEPROMs, which are semiconductor devices. FIG. 1 is an aerial pattern diagram of a conventional nonvolatile semiconductor memory. FIG. 2 is a schematic cross-sectional diagram cut along the line I-I of FIG. 1. FIG. 3 is a schematic cross-sectional diagram cut along the line II-II of FIG. 1. FIG. 4 is a schematic cross-sectional diagram cut along the line III-III of FIG. 1. In addition, FIG. 5 is an aerial pattern diagram for describing the data transfer line contacts CB being short-circuited due to a decrease in the lithographic margin in the conventional nonvolatile semiconductor memory. FIG. 6 is an aerial pattern diagram for describing the data transfer line contacts CB and interconnects being short-circuited due to a decrease in the alignment margin in the conventional nonvolatile semiconductor memory. On the other hand, FIG. 7A is an aerial pattern diagram for describing an open circuit failure in data transfer lines due to decrease in the lithographic margin in the conventional nonvolatile semiconductor memory, and FIG. 7B is an aerial pattern diagram for describing a short-circuit failure in data transfer lines due to a decrease in the lithographic margin in the conventional nonvolatile semiconductor memory. In addition, FIG. 8 is an aerial pattern diagram for describing a contact open circuit failure due to a decrease in the alignment margin needed when directly connecting via contacts in the conventional nonvolatile semiconductor memory, and FIG. 8A schematically shows a normal short-circuit, and FIG. 8B schematically shows a contact open circuit failure.
As shown in FIGS. 1 and 2, memory cells 20 are serially arranged having a NAND structure, and isolated from each other by interlayer insulator films 24. Circular or elliptical contacts (CB, CS, 16) are aligned perpendicular to data transfer lines BL. As shown in FIG. 4, the contacts are aligned along the line III-III in extremely close intervals of 2 to 3F where F denotes the minimum fabrication dimension depending on the widths of a device region and a device isolating region. On the other hand, as shown in FIG. 2, the contacts are aligned along the line I-I, which is orthogonal to the line III-III, in longer intervals than the contacts along the line III-III, for example, 40 to 100 F in the case of a NAND flash memory, for example, as described in Japanese Patent Application Laid-open No. 2000-91546.
A more sufficient lithographic margin must be secured as miniaturization increases. However, conventionally, as shown in the aerial view of FIG. 1, fringes are formed on data transfer line extended regions 14 such that via contacts 16 are always formed on parts of interconnect layers, which are to form the data transfer line extended regions 14, preventing the via contacts 16 from being over-etched due to misalignment. This arrangement requires the data transfer line extended regions 14 to form a pattern where via contact 16 portions are larger than data transfer line contact CB portions, resulting in a need for two-dimensional lithography resolution, which is unnecessary for a simple linear pattern or a hole pattern. As a result, to provide the minimum line width F of interconnects for the data transfer line extended regions 14 at the data transfer line contact CB portions, it is necessary to extend the data transfer line contacts CB along the data transfer lines BL. Therefore, a pattern length of 7 F or longer is needed for a design rule of 0.13 m or shorter, for example. In particular, the shorter the minimum line width F is made, the lower the resolution becomes in the direction orthogonal thereto, resulting in longer data transfer line contacts CB along data transfer lines 57.
Conventionally, the data transfer line contacts CB and the via contacts 16 are filled with phosphorus (P) or the like highly-doped polycrystalline silicon or a metal such as tungsten, and the interconnect layers are filled with a metal such as tungsten. Here, the data transfer line extended regions 14 being longer than 7 F along the data transfer lines 57 are assumed as the interconnect layers. Alternatively, a longer, linear fine metal pattern is naturally available, and the following description holds true with a configuration where the via contacts 16 and the data transfer line extended regions 14 are omitted, and contacts are directly formed on the data transfer lines BL regarding the data transfer lines BL as the interconnects.
Next, the case of the data transfer line contacts CB being aligned with pitches of 2 F along the line III-III is considered. When each of the data transfer line contacts CB has a certain aspect ratio such as 3 or greater, as with the conventional example, the diameter of each of the tops of the contacts along the line III-III becomes longer than F. This is because the diameter at the bottom, along the line III-III, needs to be approximately F to secure sufficient contact area with a well region 26 at each of the bottoms of the contacts, and the data transfer line contacts CB need to be in a forward tapered shape so that the diameter of each of the tops of the contacts along the line III-III can be longer, which allows those data transfer line contacts CB to be completely filled. On the other hand, the width of each interconnect, which makes contact with the contact for the interconnect layer formed on the top of that contact, is conventionally less than F. This is also caused even when forming a forward tapered-shape region to secure a metal filling layer in the data transfer line extended regions 14 and secure margins in a closely adjacent contact pattern. As a result, the width of each interconnect is shorter than the diameter of each contact in the cross section cutting along a line perpendicular to the data transfer lines BL (the cross section along the line III-III).
A first problem of decreasing the inter-contact short-circuit margin is raised in the inter-contact short-circuit margin because of conducting wet etching twice for the contacts: the first wet etching is carried out to remove residue left on the tops of the data transfer line contacts CB after anisotropic etching for the contacts; and the second wet etching is carried out to remove residue left after anisotropic etching the data transfer lines (see FIG. 5). In addition, another problem is a short-circuit between the contacts and the data transfer lines due to a decrease in the alignment margin resulting from an increase in the diameter of each contact due to wet etching (see FIG. 6).
A second problem is an open/short failure in the interconnects due to a decrease in the lithographic margin for the variously-shaped data transfer lines as shown in FIGS. 7A and 7B. FIGS. 7A and 7B show exemplary open circuit failure portions 36 and exemplary short-circuit failure portions 38, respectively. The conventional technology simultaneously forming ladle-shaped data transfer lines as described above as well as normal line and space patterns using one lithography process, cannot maintain a sufficient focal depth for both patterns, and also cannot perform a very fine process while maintaining a sufficient exposure fluctuation-tolerable width for extremely miniaturized devices. This is apparent from the fact that the minimum line width in two directions at the resolution limit cannot be simultaneously obtained since the spatial frequency of the light intensity in an arbitrary direction is equal to or less than the so-called resolution limit. Therefore, usage of an exposure device with deep focal depth and optimization of complex optical dimension correction (OPC) for the ladle-shaped handgrip portion are needed.
In addition, since the distance between the interconnects and opposing data transfer line extended regions 14 further greatly influences a lithographic margin as miniaturization increases, it becomes necessary to form longer opposing data transfer line extended regions 14 in a zigzag shape along the line I-I shown in FIG. 1. Therefore, the data transfer line extended regions 14 are formed overlapping the memory cells. In this case, since the data transfer line extended regions 14 are close to the memory cells, the degree of influence from the potential of the data transfer lines BL on each memory cell differs depending on whether or not the data transfer line extended regions 14 are above the memory cells when data is written/read. This creates a problem of change in the write/read voltages to/from memory cells due to the capacitive coupling, resulting in large fluctuation in threshold distribution. FIG. 3 schematically shows an example where the source line contacts CS partially overlap device isolating regions 30, and short-circuited portions 28 are formed between the source line contacts CS and the p-well regions. Moreover, FIG. 4 schematically shows an example of the short-circuited portions 32 between the data transfer line contacts CB and the p-well regions 26, and decreased margin portions 34 between the data transfer line contacts CB and the interconnects (data transfer line extended regions 14).